Modern-day electronics require multiple patterned layers of electrically or optically active materials, sometimes over a relatively large substrate. Electronics such as radio frequency identification (RFID) tags, photovoltaics, optical and chemical sensors all require some level of patterning in their electronic circuitry. Flat panel displays, such as liquid crystal displays or electroluminescent displays (for example, OLED), rely upon accurately patterned sequential layers to form thin film components of the backplane. These components include capacitors, transistors, and power buses. The industry is continually looking for new methods of materials deposition and layer patterning for both performance gains and cost reductions. Thin film transistors (TFTs) are one common electronic component, and can serve to illustrate the manufacturing issues for many thin film components. TFTs are widely used as switching elements in electronics, for example, in active-matrix liquid-crystal displays, smart cards, and a variety of other electronic devices and components thereof.
In the past decade, various materials have received attention as a potential alternative to amorphous silicon for use in semiconductor channels of thin film transistors. Semiconductor, dielectric, conducting, and protective materials that are simpler to process are desirable, especially those that are capable of being applied to large areas by relatively simple processes. The discovery of practical inorganic semiconductors as a replacement for current silicon-based technologies has also been the subject of considerable research efforts. For example, metal oxide semiconductors are known that constitute zinc oxide, indium oxide, gallium indium zinc oxide, tin oxide, or cadmium oxide deposited with or without additional doping elements including metals such as aluminum. Such semiconductor materials, which are transparent, can have an additional advantage for certain applications.
A semiconductor material useful in a TFT must display several characteristics. In typical applications of a thin film transistor, the desire is for a switch that can control the flow of current through the device. As such, it is desired that when the switch is turned on a high current can flow through the device. The extent of current flow is related to the semiconductor charge carrier mobility. When the device is turned off, it is desired that the current flow be very small. The ratio between current flow in the on state to current flow in the off state is related to the native charge carrier concentration. It is further desired that the device remain unchanged during operation. The stability of transistors is typically evaluated by holding the device under a constant stress (or bias) that is consistent with the stress applied to the transistor in operation for a given application.
Many electronic devices benefit from the presence of either a passivation layer or a barrier layer or both. Thin film metal oxide TFTs, such as ZnO, GIZO, or GZO, have instabilities that can limit their adoption in practical applications. There has been a concerted effort recently to improve the stability of these types of TFTs with passivation layers. Typical passivation layer structures employ inorganic thin films as the passivation layer, such as Al2O3. The use of these inorganic passivation layers typically induces a negative threshold shift that can be undesirable. Complicated processing schemes have been introduced to passivate with inorganic materials without threshold shifts. Alternatively, researchers have used multilayer channels to modify the charge on the back channel, for instance using two different stoichiometries of IGZO for the semiconductor layer. There has been limited work done to passivate inorganic TFTs with photopatternable polymers, with varied response. In most cases, a negative shift in threshold voltage is still present with passivation and the processing involves the complex multistep process associated with photolithography and additional post deposition annealing steps. There remains a need for a passivation process for metal oxide transistors which is simple, and which results in TFTs stable under bias stress without an associated shift in threshold shift from the unpassivated state.
Furthermore, it is recognized in the art that the material that is in contact with the back channel of a semiconductor has an impact on the performance of the transistor. In the aforementioned cases, the passivation layer is deposited on the back channel of a bottom gate device. In other architectures, controlling the back channel interface is still important even when the material layer does not impact the environmental stability of the device. For instance, in the case of top gate TFTs it has been observed that ZnO-based transistors built on glass have very negative threshold voltages. There remains a need for device structures and material layers that control the back channel interface in all types of device architectures including bottom gate transistors, top gate transistors, and vertical transistors.
Atomic layer deposition (ALD) can be used as a fabrication step for forming a number of types of thin-film electronic devices, including semiconductor devices and supporting electronic components such as resistors and capacitors, insulators, bus lines, and other conductive structures. ALD is particularly suited for forming thin layers of metal oxides in the components of electronic devices. General classes of functional materials that can be deposited with ALD include conductors, dielectrics or insulators, and semiconductors. Examples of useful semiconducting materials are compound semiconductors such as gallium arsenide, gallium nitride, cadmium sulfide, zinc oxide, and zinc sulfide. A dielectric material is any material that is a poor conductor of electricity, often also referred to as an insulator material. Such materials typically exhibit a bulk resistivity greater than 1010 Ω-cm. Examples of dielectrics are SiO2, HfO, ZrO, SiNx, and Al2O3.
There has been growing interest in combining ALD with a technology known as selective area deposition (SAD). As the name implies, selective area deposition involves treating portion(s) of a substrate such that a material is deposited only in those areas that are desired, or selected. These methods have been used to fabricate devices, as described in Appl. Phys. Lett. 2013, 103 (4), 043505 by Levy, et. al. There are many potential advantages to selective area deposition techniques, such as eliminating an etch process for film patterning, reduction in the number of cleaning steps required, and patterning of materials which are difficult to etch. There, however, persists a problem of combining multiple SAD steps to form working devices, in combination with organic elements in a device. In some device architectures, the removal of the inhibitor used in selective area deposition can damage or otherwise negatively impact the underlying layer. There remains a need for methods to fabricate devices with organic elements as well as SAD methods that do not require the removal of the deposition inhibitor.
Accordingly, there still remains a need for high-quality passivation and back channel control layers that result in stable, high-quality devices and that can be formed with simple processing methods. Correspondingly, a method is needed to simply pattern this layer for easy device integration. Furthermore there is a need for novel processes for forming multilayer insulating structures using selective area processes.